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72 AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
33234H
4.2.3.2 Statistic Mask (STATISTIC_MASK[0:3]
Descriptor Statistic Mask (STATISTIC_MASK[0])
Descriptor Statistic Mask (STATISTIC_MASK[1])
Descriptor Statistic Mask (STATISTIC_MASK[2])
Descriptor Statistic Mask (STATISTIC_MASK[3])
MSR Address GLIU0: 100000A1h
GLIU1: 400000A1h
Typ e R /W
Reset Value 00000000_00000000h
MSR Address GLIU0: 100000A5h
GLIU1: 400000A5h
Typ e R /W
Reset Value 00000000_00000000h
MSR Address GLIU0: 100000A9h
GLIU1: 400000A9h
Type R /W
Reset Value 00000000_00000000h
MSR Address GLIU0: 100000ADh
GLIU1: 400000ADh
Type R /W
Reset Value 00000000_00000000h
STATISTIC_MASK[0:3] Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
IOD_MASK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P2D MASK
STATISTIC_MASK[0:3] Bit Descriptions
Bit Name Description
63:32 IOD_MASK Mask for Hits to Each IOD. Hits are determined after the request is arbitrated. A hit is
determined by the following logical equation: Hit = |(IOD_MASK[n-1:0] &
RQ_DESC_HIT[n-1:0] && is_io) | |(P2D_MASK[n-1:0] & RQ_DESC_HIT[n-1:0] &&
is_mem).
31:0 P2D_MASK Mask for Hits to Each P2D. A hit is determined by the following logical equation: Hit =
|(IOD_MASK[n-1:0] & RQ_DESC_HIT[n-1:0] && is_io) | |(P2D_MASK[n-1:0] &
RQ_DESC_HIT[n-1:0] && is_mem).