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AMD Geode™ LX Processors Data Book 69
GLIU Register Descriptions
33234H
4.2.2.11 GLIU Slave Disable (GLIU_SLV)
The slave disable registers are available for the number of ports on the GLIU. The unused ports return 0.
MSR Address GLIU0: 1000008Ch
GLIU1: 4000008Ch
Typ e R /W
Reset Value 00000000_00000000h
GLIU_SLV Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
SLAVE_DIS7
SLAVE_DIS6
SLAVE_DIS5
SLAVE_DIS4
SLAVE_DIS3
SLAVE_DIS2
SLAVE_DIS1
SLAVE_DIS0
GLIU_SLV Bit Descriptions
Bit Name Description
63:8 RSVD Reserved.
7 SLAVE_DIS7 Slave Transactions Disable for Port 7. (GLIU0 = Not Used; GLIU1 = Not Used.) Write
1 to disable slave transactions to Port 7.
6 SLAVE_DIS6 Slave Transactions Disable for Port 6. (GLIU0 = Not Used; GLIU1 = SB.) Write 1 to
disable slave transactions to Port 6.
5 SLAVE_DIS5 Slave Transactions Disable for Port 5. (GLIU0 = GP; GLIU1 = VIP.) Write 1 to disable
slave transactions to Port 5.
4 SLAVE_DIS4 Slave Transactions Disable for Port 4. (GLIU0 = DC; GLIU1 = GLPCI.) Write 1 to dis-
able slave transactions to Port 4.
3 SLAVE_DIS3 Slave Transactions Disable for Port 3. (GLIU0 = CPU Core; GLIU1 = GLCP.) Write 1
to disable slave transactions to Port 3.
2 SLAVE_DIS2 Slave Transactions Disable for Port 2. (GLIU0 = Interface to GLIU1; GLIU1 = VP.)
Write 1 to disable slave transactions to Port 2.
1 SLAVE_DIS1 Slave Transactions Disable for Port 1. (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
Write 1 to disable slave transactions to Port 1.
0 SLAVE_DIS0 Slave Transactions Disable for Port 0. (GLIU0 = GLIU; GLIU1 = GLIU.) Write 1 to dis-
able slave transactions to Port 0.