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AMD Geode™ LX Processors Data Book 123
CPU Core Register Descriptions
33234H
5.5.2.14 IF Built-In Self-Test MSR (IF_BIST_MSR)
IF_BIST_MSR may be used to run built-in self-test (BIST) on the IF Tag and Target RAMs, and to get an indication of
whether the BIST run passed or failed. There are separate BIST controllers for the Tag RAM and for the Target RAMs. A
MSR read of IF_BIST_MSR causes BIST to be run.
IF_BIST_MSR can only be run when the level-1 COF cache, the level-0 COF cache, and the return stack is disabled in the
IF_CONFIG MSR. If the COF cache is enabled, reading IF_BIST_MSR does not cause BIST to be run, and returns zero.
After BIST has been run by reading IF_BIST_MSR, the contents of the IF Tag RAMs is invalidated (cleared).
MSR Address 00001140h
Typ e RO
Reset Value 00000000_00000000h
IF_BIST_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD
TGT_PASS
TAG_PASS
IF_BIST_MSR Bit Descriptions
Bit Name Description
63:2 RSVD Reserved.
1TGT_PASS Target RAM BIST Status.
0: Target RAM BIST did not pass. (Default)
1: Target RAM BIST passed.
0TAG_PASS Tag RAM BIST Status.
0: Tag RAM BIST did not pass. (Default)
1: Tar RAM BIST passed.