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150 AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.51 Instruction Memory Configuration MSR (IM_CONFIG_MSR)
MSR Address 00001700h
Typ e R /W
Reset Value 00000000_00000000h
IM_CONFIG_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
LOCK RSVD
DRT
RSVD
ABSE
EBE
RSVD
ICD
TUS
RSVD
L0D
L0IN
RSVD
SER
FLD
TBE
IM_CONFIG_MSR Bit Descriptions
Bits Name Description
63:32 RSVD Reserved. (Default = 0)
31:24 LOCK Lock. Locks ways of the instruction cache from being allocated or replaced on an
instruction cache miss. If all ways are locked, caching is effectively disabled.
Bit 31: Ways 15 & 14
Bit 30: Ways 13 & 12
Bit 29: Ways 11 & 10
Bit 28: Ways 9 & 8
Bit 27: Ways 7 & 6
Bit 26: Ways 5 & 4
Bit 25: Ways 3 & 2
Bit 24: Ways 1 & 0
0: Not locked. (Default)
1: Locked
23:17 RSVD Reserved.
16 DRT Dynamic Retention Test. Allow dynamic retention test for BIST of tag array.
0: Disable. (Default)
1: Enable.
15:12 RSVD Reserved. (Default = 0)
11 ABSE Aborts for Speculative Instruction Fetch Requests Enable. Enable aborts for specu-
lative IF requests for which there is an L1 TLB miss. IM passes the speculative informa-
tion from IF directly to DM. DM responds in one of four ways:
Returns page if it hits in the L2.
Returns abort if it does not hit in the L2 and it a speculative request.
Returns a retry if it does not hit in the L2 and it was a non-speculative request and the
pipe is not idle,
Does a tablewalk if it does not hit in the L2 and it was a non-speculative request and the
pipe is idle.
0: Disable. (Default)
1: Enable.
10 EBE Instruction Memory Eviction Bus Enable. The default is to have IM evictions disabled.
This bit should be set when the L2 cache is enabled, since the L2 cache operates exclu-
sively in Victim mode.
0: Disable. Invalidate clean cache lines when replaced, do not evict. (Default)
1: Enable. Evict clean cache lines when they are replaced.
9 RSVD Reserved.