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AMD Geode™ LX Processors Data Book 549
GeodeLink™ Control Processor Register Descriptions
33234H
6.14.2.7 GLCP DOWSER (GLCP_DOWSER)
6.14.2.8 GLCP I/O Delay Controls (GLCP_DELAY_CONTROLS)
MSR Address 4C00000Eh
Typ e R /W
Reset Value 00000000_00000000h
GLCP_DOWSER Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
SW Defined
313029282726252423222120191817161514131211109876543210
SW Defined
GLCP_DOWSER Bit Descriptions
Bit Name Description
63:0 --- Software Defined. This 64-bit scratchpad register was specifically added for SW
debugger use (DOWSER). The register resets to zero with both hard and soft resets.
MSR Address 4C00000Fh
Typ e R /W
Reset Value 00000000_00000000h
GLCP_DELAY_CONTROLS Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
EN
B_DQ
B_CMD
B_MA
SDCLK_SET
DDR_RLE
SDCLK_DIS
TLA1_OA
D_TLA1
D_TLA0
D_DQ_E
D_DQ_O
RSVD
D_SDCLK
D_CMD_O
D_CMD_E
D_MA_O
D_MA_E
313029282726252423222120191817161514131211109876543210
D_PCI_O
D_PCI_E
D_DOTCLK
D_DRGB_O
D_DRGB_E
D_PCI_IN
D_TDBGI
D_VIP
D_VIPCLK
H_SDCLK
PLL_FD_DEL
RSVD
DLL_OV
DLL_OVS/RSDA
GLCP_DELAY_CONTROLS Bit Definition
Bit Name Description
63 EN 0: Use default values.
1: Use value in bits [62:0].
62 B_DQ Buffer Control for DQ[63:0], DQS[7:0], DQM[7:0], TLA[1:0] drive select.
1: Half power.
0: Quarter power.
61 B_CMD Buffer Control for RAS[1:0]#, CAS[1:0]#, CKE[1:0], CS[3:0]#, WE[1:0]# drive select.
1: Half power.
0: Quarter power.
60 B_MA Buffer Control for MA[13:0] and BA[1:0].
0: Half power.
1: Full power.