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AMD Geode™ LX Processors Data Book 637
Instruction Set
33234H
IMUL Integer (Signed) Multiply x---xxuux b h
Accumulator by Register/Memory
Multiplier: Byte
Word
Doubleword
F [011w] [mod 101 r/m]
3
4
4
3
4
4
Register with Register/Memory
Multiplier: Word
Doubleword
0F AF [mod reg r/m]
4
4
4
4
Register/Memory with Immediate to Register2
Multiplier: Byte
Word
Doubleword
6 [10s1] [mod reg r/m] ###
4-6
4-7
4-7
4-6
4-7
4-7
IN Input from I/O Port --------- m
Fixed Port E [010w] # 7 7/21
Variable Port E [110w] 7 7/21
INC Increment by 1 x---xxxx- b h
Register/Memory F [111w] [mod 000 r/m] 1 1
Register (short form) 4 [0 reg] 1 1
INS Input String from I/O Port 6 [110w] 10 10/24 --------- b h,m
INT i Software Interrupt CD # 23 37-245 --x0----- b,e g,j,k,r
INT 3 Breakpoint Software Interrupt CC 21-22 37-245 b,c g,i,k,r
INTO Overflow Software Interrupt
If OF==0
If OF==1 (INT 4)
CE
4
7
4
7
b,c g,i,k,r
INVD Invalidate Cache 0F 08 9+ 9+ --------- t t
INVLPG Invalidate TLB Entry 0F 01 [mod 111 r/m] 7+ 7+ ---------
IRET Interrupt Return CF 6-13 13-239 xxxxxxxxx g,h,j,k,
r
JB/JNAE/JC Jump on Below/Not Above or Equal/Carry --------- r
8-bit Displacement 72 + 1 1
Full Displacement 0F 82 +++ 1 1
JBE/JNA Jump on Below or Equal/Not Above -------- r
8-bit Displacement 76 + 1 1
Full Displacement 0F 86 +++ 1 1
JCXZ/JECXZ Jump on CX/ECX Zero E3 + 2 2 --------- r
JE/JZ Jump on Equal/Zero -------- r
8-bit Displacement 74 + 1 1
Full Displacement 0F 84 +++ 1 1
JL/JNGE Jump on Less/Not Greater or Equal -------- r
8-bit Displacement 7C + 1 1
Full Displacement 0F 8C +++ 1 1
JLE/JNG Jump on Less or Equal/Not Greater -------- r
8-bit Displacement 7E + 1 1
Full Displacement 0F 8E +++ 1 1
JMP Unconditional Jump -------- b h,j,k,r
8-bit Displacement EB + 1 1
Full Displacement E9 +++ 1 1
Register/Memory Indirect Within Segment FF [mod 100 r/m] 1/3 1/3
Direct Intersegment EA [unsigned full offset,
selector]
79-254
Indirect Intersegment FF [mod 101 r/m] 9 11-256
JNB/JAE/JNC Jump on Not Below/Above or Equal/Not Carry -------- r
8-bit Displacement 73 + 1 1
Full Displacement 0F 83 +++ 1 1
Table 8-26. Processor Core Instruction Set (Continued)
Instruction Opcode
Clock Count
(Reg/Cache Hit) Flags
Notes
Real
Mode
Prot’d
Mode
ODI TSZ APC
FFFFFFFFF
Real
Mode
Prot’d
Mode