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AMD Geode™ LX Processors Data Book 547
GeodeLink™ Control Processor Register Descriptions
33234H
6.14.2.3 Chip Fabrication Information (GLCP_FAB)
This read only register is used to track various fab, process, and product family parameters. It is meant for AMD internal use
only. Reads return reset value.
6.14.2.4 GLCP Global Power Management Controls (GLCP_GLB_PM)
MSR Address 4C00000Ah
Typ e RO
Reset Value 00000000_00000001h
MSR Address 4C00000Bh
Typ e R /W
Reset Value 00000000_00000000h
GLCP_GLB_PM Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD
DOTPLL_EN
SYSPLL_EN
RSVD
OUT_VP
OUT_GIO
OUT_GLMC
OUT_PCI
OUT_OTHER
RSVD
CLK_DLY_EN
CLK_DIS_EN
RSVD
RSVD
THT_EN
GLCP_GLB_PM Bit Descriptions
Bit Name Description
63:18 RSVD Reserved.
17 DOTPLL_EN DOTPLL Enable. Enables turning off the Dot clock PLL during sleep when high.
16 SYSPLL_EN SYSPLL Enable. Enables turning off the system PLLs during sleep when high.
15:13 RSVD Reserved.
12 OUT_VP VP Outputs. When set, enables VP outputs to TRI_STATE during a sleep sequence.
11 OUT_GIO GIO Outputs. When set, enables AMD Geode™ I/O companion (GIO) to TRI_STATE
device outputs during a sleep sequence.
10 OUT_GLMC GLMC Outputs. When set, enables GLMC to TRI_STATE outputs during a sleep
sequence.
9OUT_PCI GLPCI Outputs. When set, enables GLPCI to TRI_STATE outputs during a sleep
sequence.
8OUT_OTHEROther Outputs. When set, enables TDBGO and SUSPA# to TRI_STATE during a sleep
sequence.
7:5 RSVD Reserved.
4 CLK_DLY_EN Clock Delay Enable. Enables gating off clock enables from a delay rather than
GLCP_CLK4ACK (MSR 4C000013h) when high.
3 CLK_DIS_EN Clock Display Enable. Enables the assertion of internal signal, mb_clk_dis_req, during
a sleep sequence when high.
2:1 RSVD Reserved.
0THT_EN Throttle Enable. Enables processor throttling functions. If this bit is low, all the functions
related to throttling are disabled (GLCP_TH_OD, GLCP_CNT, etc.).