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AMD Geode™ LX Processors Data Book 53
GLIU Register Descriptions
33234H
GLIU0: 100000DEh
GLIU1: 400000DEh
R/W Data Compare Mask Low
(DA_COMPARE_MASK_LO[3])
00000000_00000000h Page 78
GLIU0: 100000DFh
GLIU1: 400000DFh
R/W Data Compare Mask High
(DA_COMPARE_MASK_HI[3])
00000000_00000000h Page 79
Table 4-7. GLIU Statistic and Comparator MSRs Summary (Continued)
MSR Address Type Register Reset Value Reference
Table 4-8. GLIU P2D Descriptor MSRs Summary
MSR Address Type Register Reset Value Reference
GLIU0
10000020h-
10000025h
R/W P2D Base Mask Descriptor
(P2D_BM): P2D_BM[5:0]
000000FF_FFF00000h Page 80
10000026h-
10000027h
R/W P2D Base Mask Offset Descriptor
(P2D_BMO): P2D_BMO[1:0]
00000FF0_FFF00000h Page 81
10000028h R/W P2D Range Descriptor (P2D_R:
P2D_R[0]
00000000_000FFFFFh Page 82
10000029h-
1000002Bh
R/W P2D Range Offset Descriptor
(P2D_RO): P2D_RO[2:0]
00000000_000FFFFFh Page 83
1000002Ch R/W P2D Swiss Cheese Descriptor
(P2D_SC): P2D_SC[0]
00000000_00000000h Page 84
1000002Dh-
1000003Fh
R/W P2D Reserved Descriptors --- ---
GLIU1
40000020h-
40000029h
R/W P2D Base Mask Descriptor
(P2D_BM): P2D_BM[9:0]
000000FF_FFF00000h Page 80
4000002Ah-
4000002Dh
R/W P2D Range Descriptor (P2D_R):
P2D_R[3:0]
00000000_000FFFFFh Page 82
4000002Eh R/W P2D Swiss Cheese Descriptor
(P2D_SC): P2D_SC[0]
00000000_00000000h Page 84
4000002Fh-
4000003Fh
R/W P2D Reserved Descriptor
(P2D_RSVD)
00000000_00000000h ---
Table 4-9. GLIU Reserved MSRs Summary
MSR Address Type Register Reset Value Reference
GLIU0: 10000006h-
1000000Fh
GLIU1: 40000006h-
4000000Fh
R/W Reserved for future use by AMD. 00000000_00000000h ---
GLIU0: 10000040h-
1000004Fh
GLIU1: 40000040h-
4000004Fh
R/W Reserved for future use by AMD. 00000000_00000000h ---
GLIU0: 10000050h-
1000007Fh
GLIU1: 40000050h-
4000007Fh
R/W Reserved for future use by AMD. 00000000_00000000h ---