Filter
Top Products
CHAPTER 2 V
R
4120A
Preliminary User’s Manual S15543EJ1V0UM
107
The User segment starts at address 0 and the current active user process resides in either useg (in 32-bit mode) or
xuseg (in 64-bit mode). The TLB identically maps all references to useg/xuseg from all modes, and controls cache
accessibility.
The processor operates in User mode when the Status register contains the following bit-values:
KSU = 10
EXL = 0
ERL = 0
In conjunction with these bits, the UX bit in the Status register selects addressing mode as follows:
When UX = 0, 32-bit useg space is selected.
When UX = 1, 64-bit xuseg space is selected.
Table 2-27 lists the characteristics of each user segment (useg and xuseg).
Table 2-27. Comparison of useg and xuseg
Address Bit Status Register Bit Value Segment Address Range Size
Value KSU EXL ERL UX Name
32-bit
A31 = 0
10 0 0 0 useg 0000_0000H
to
7FFF_FFFFH
2 Gbytes
(2
31
bytes)
64-bit
A(63:40) = 0
10 0 0 1 xuseg 0000_0000_0000_0000H
to
0000_00FF_FFFF_FFFFH
1 Tbyte
(2
40
bytes)
(1) useg (32-bit mode)
In User mode, when UX = 0 in the Status register and the most significant bit of the virtual address is 0, this virtual
address space is labeled useg.
Any attempt to reference an address with the most-significant bit set while in User mode causes an Address Error
exception (see Section 2.5 Exception Processing).
The TLB Mismatch exception vector is used for TLB misses.
(2) xuseg (64-bit mode)
In User mode, when UX = 1 in the Status register and bits 63 to 40 of the virtual address are all 0, this virtual
address space is labeled xuseg.
Any attempt to reference an address with bits 63 to 40 equal to 1 causes an Address Error exception (see Section
2.5 Exception Processing).
The XTLB Mismatch exception vector is used for TLB misses.