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CHAPTER 7 PCI CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM
375
(2) Non delayed read transaction
When IDRTD bit in P_BCNT register is ‘1’, the PCI Controller uses “Non Delayed Read Transaction” rule for read
transactions from Internal bus-side to PCI-side. In this mode, burst transfers are disconnected at every single word.
The rule is as follows;
<1> An internal bus block connecting to the internal bus issues the read transaction to an external PCI target
device.
<2> The PCI Controller inserts waits before the first data transfer on the internal bus.
<3> The PCI Controller issues the read transaction to the external PCI target device.
<4> The PCI target device accepts this access.
<5> The PCI Controller returns the read 1-word data to internal bus block. At the same time, the PCI Controller
issues “disconnect” to internal bus block when the block tries to continue the burst read transaction. The
internal bus block must terminate the transaction as soon as possible.
Figure 7-5. Non Delayed Read Transaction from Internal Bus to PCI
PCI
Controller
PCI
Target
Device
Internal
Bus Block
<1>
<4>
<2>
<3>
<5>
When the PCI Controller receives target abort/master abort on PCI bus after it has accepted non-delayed-read
from an external PCI device, it sets RTABT/RMABT bit of P_IGSR register and RDTAT/RDMAT bit of P_PGSR
register, and issues interrupts to an external PCI-Host device and the VR
4120A (if not masked). Then, the PCI
Controller returns all “0” word to internal bus block and issues “disconnect” when the internal bus block issues the
burst transfer.