APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM
513
LUI
Load Upper Immediate
LUI
0
0 0 0 0 0
LUI
0 0 1 1 1 1
rt immediate
31 26 25 21 20 16 15 0
655 16
Format:
LUI rt, immediate
Description:
The 16-bit
immediate
is shifted left 16 bits and concatenated to 16 bits of zeros. The result is placed into general
register
rt
. In 64-bit mode, the loaded word is sign-extended.
Operation:
32 T:
GPR [rt] ← immediate || 0
16
64 T:
GPR [rt] ← (immediate
15
)
32
|| immediate || 0
16
Exceptions:
None