Filter
Top Products
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM
495
ERET
Exception Return
ERET
CO
1
COP0
0 1 0 0 0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ERET
0 1 1 0 0 0
31 26 25 24 6 5 0
61 19 6
Format:
ERET
Description:
ERET is the instruction for returning from an interrupt, exception, or error trap. Unlike a branch or jump instruction,
ERET does not execute the next instruction.
ERET must not itself be placed in a branch delay slot.
If the processor is servicing an error trap (
SR2
= 1), then load the PC from the ErrorEPC register and clear the
ERL
bit of the Status register (
SR2
). Otherwise (
SR2
= 0), load the PC from the EPC register, and clear the
EXL
bit of
the Status register (
SR1
= 0).
When a MIPS16 instruction can be executed, the value of clearing the least significant bit of the EPC or error EPC
register to 0 is loaded to PC. This means the content of the least significant bit is reflected on the ISA mode bit
(internal).
Operation:
32, 64 T: if SR
2
= 1 then
if MIPS16EN = 1 then
PC ← ErrorEPC
63..1
|| 0
ISA MODE ← ErrorEPC
0
else
PC ← ErrorEPC
endif
SR ← SR
31..3
|| 0 || SR
1..0
else
if MIPS16EN = 1 then
PC ← EPC
63..1
|| 0
ISA MODE ← EPC
0
else
PC ← EPC
endif
SR ← SR
31..2
|| 0 || SR
0
endif
Exceptions:
Coprocessor unusable exception