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CHAPTER 2 V
R
4120A
120
Preliminary User’s Manual S15543EJ1V0UM
2.4.5.3 EntryLo0 (2) and EntryLo1 (3) registers
The EntryLo register consists of two registers that have identical formats: EntryLo0, used for even virtual pages
and EntryLo1, used for odd virtual pages. The EntryLo0 and EntryLo1 registers are both read-/write-accessible. They
are used to access the on-chip TLB. When a TLB read/write operation is carried out, the EntryLo0 and EntryLo1
registers hold the contents of the low-order 32 bits of TLB entries at even and odd addresses, respectively.
Figure 2-36. EntryLo0 and EntryLo1 Registers
2728
EntryLo1
EntryLo0
EntryLo1
EntryLo0
224
031 56 3 2 1
0 PFN C D V G
13 1 1
2728
224
0
31 56 3 2 1
0
PFN C D V G
13 1 1
(a) 32-bit mode
(b) 64-bit mode
2728
2236
063 56 3 2 1
0 PFN C D V G
13 1 1
2728
2236
063 56 3 2 1
0
PFN C D V G
13 1 1
PFN : Page frame number; high-order bits of the physical address.
C : Specifies the TLB page attribute (see Table 2-33).
D : Dirty. If this bit is set to 1, the page is marked as dirty and, therefore, writeable. This bit is actually a
write-protect bit that software can use to prevent alteration of data.
V : Valid. If this bit is set to 1, it indicates that the TLB entry is valid; otherwise, a TLB Invalid exception
(TLBL or TLBS) occurs.
G : Global. If this bit is set in both EntryLo0 and EntryLo1, then the processor ignores the ASID during TLB
lookup.
0 : RFU. Write 0 in a write operation. When this field is read, 0 is read.
The coherency attribute (C) bits are used to specify whether to use the cache in referencing a page. When the
cache is used, whether the page attribute is “cached” or “uncached” is selected by algorithm.
Table 2-32 lists the page attributes selected according to the value in the C bits.