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CHAPTER 7 PCI CONTROLLER
380
Preliminary User’s Manual S15543EJ1V0UM
(2) Non delayed read transaction
When PDRTD bit in P_BCNT register is ‘1’, the PCI Controller uses “Non Delayed Read Transaction” rule for read
transactions from Internal bus-side to PCI-side. In this mode, burst transfers are disconnected at every single word.
The rule is as follows;
<1> PCI master device issues the read transaction to internal bus target block.
<2> The PCI Controller responds to this access by asserting DEVSEL_B, but the PCI Controller does not assert
TRDY_B at this moment.
<3> The PCI Controller issues the read transaction to internal bus target block
<4> The internal bus target block accepts this access and the PCI Controller read a word from it.
<5> The PCI Controller asserts TRDY_B and return the 1-word data to PCI master device. Then, the PCI
Controller issues “disconnect” to PCI master device when it issues the burst transfer. The PCI master
device must terminates the transaction as soon as possible.
Figure 7-9. Non Delayed Read Transaction from PCI to Internal bus
PCI
Controller
PCI
Master
Device
Internal
Bus Block
<1>
<4>
<2>
<3>
<5>
When the PCI Controller receives Bus Error on internal bus after it accepts delayed-read from PCI-side, it sets
IRBER bit of P_IGSR register and PRBER bit of P_PGSR register, and reports by interrupts to an external PCI-Host
device and the VR
4120A (if not masked). Then, the PCI Controller returns all “0” word to PCI master device and
issues “disconnect” when PCI master device issues the burst transfer.