Filter
Top Products
APPENDIX A MIPS III INSTRUCTION SET DETAILS
548
Preliminary User’s Manual S15543EJ1V0UM
SLLV
Shift Left Logical Variable
SLLV
SPECIAL
0 0 0 0 0 0
rt rd
0
0 0 0 0 0
SLLV
0 0 0 1 0 0
31 26 25 21 20 16 15 11 10 6 5 0
6 5555 6
rs
Format:
SLLV rd, rt, rs
Description:
The contents of general register
rt
are shifted left the number of bits specified by the low-order five bits contained in
general register
rs
, inserting zeros into the low-order bits.
The result is placed in register
rd
.
In 64-bit
mode, the 32-bit result is sign-extended when placed in the destination register. It is sign extended for all
shift amounts, including zero; SLLV with zero shift amount truncates a 64-bit value to 32 bits and then sign extends
this 32-bit value. SLLV, unlike nearly all other word operations, does not require an operand to be a properly sign-
extended word value to produce a valid sign-extended word result.
Operation:
32 T:
s ← GPR [rs]
4...0
GPR [rd] ← GPR [rt]
(31 - s)...0
|| 0
s
64 T:
s ← 0 || GPR [rs]
4...0
temp ← GPR [rt]
(31 - s)...0
|| 0
s
GPR [rd] ← (temp
31
)
32
|| temp
Exceptions:
None
Caution SLLV with a shift amount of zero may be treated as a NOP by some assemblers, at some
optimization levels. If using SLLV with a purpose of sign-extension, check the assembler
specification.