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APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM
533
MULT
Multiply
MULT
rs
SPECIAL
0 0 0 0 0 0
MULT
0 1 1 0 0 0
0
0 0 0 0 0 0 0 0 0 0
31 26 25 21 20 6 5 0
65 610
rt
5
16 15
Format:
MULT rs, rt
Description:
The contents of general registers
rs
and
rt
are multiplied, treating both operands as signed 32-bit integer. No
integer overflow exception occurs under any circumstances.
In 64-bit mode, the operands must be valid 32-bit, sign-extended values.
When the operation completes, the low-order word of the double result is loaded into special register
LO
, and the
high-order word of the double result is loaded into special register
HI
.
If either of the two preceding instructions is MFHI or MFLO, the results of these instructions are undefined. Correct
operation requires separating reads of
HI
or
LO
from writes by a minimum of two other instructions.
Operation:
32 T-2: LO
← undefined
HI
← undefined
T-1: LO
← undefined
HI
← undefined
T: t
← GPR [rs] * GPR [rt]
LO
← t
31...0
HI
← t
63...32
64 T-2: LO
← undefined
HI
← undefined
T-1: LO
← undefined
HI
← undefined
T: t
← GPR [rs]
31...0
* GPR [rt]
31...0
LO
← (t
31
)
32
|| t
31...0
HI
← (t
63
)
32
|| t
63...32
Exceptions:
None