NEC uPD98502 Network Cables User Manual


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APPENDIX A MIPS III INSTRUCTION SET DETAILS
566
Preliminary User’s Manual S15543EJ1V0UM
SWR
Store Word Right (2/3)
SWR
Operation:
32 T:
vAddr
←
((offset
15
)
16
|| offset
15...0
) + GPR [base]
(pAddr, uncached)
←
AddressTranslation (vAddr, DATA)
pAddr
←
pAddr
PSIZE - 1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
if BigEndianMem = 1 then
pAddr ← pAddr
PSIZE - 1...2
|| 0
2
endif
byte
←
vAddr
1...0
xor BigEndianCPU
2
if (vAddr
2
xor BigEndianCPU) = 0 then
data ← 0
32
|| GPR [rt]
31 – 8 * byte...0
|| 0
8 * byte
else
data ← GPR [rt]
31 – 8 * byte
|| 0
8 * byte
|| 0
32
endif
StoreMemory (uncached, WORD-byte, data, pAddr, vAddr, DATA)
64 T:
vAddr
←
((offset
15
)
48
|| offset
15...0
) + GPR [base]
(pAddr, uncached)
←
AddressTranslation (vAddr, DATA)
pAddr
←
pAddr
PSIZE - 1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
if BigEndianMem = 1 then
pAddr
←
pAddr
PSIZE - 1...2
|| 0
2
endif
byte
←
vAddr
1...0
xor BigEndianCPU
2
if (vAddr
2
xor BigEndianCPU) = 0 then
else
endif
StoreMemory (uncached, WORD-byte, data, pAddr, vAddr, DATA)
data ← 0
32
|| GPR [rt]
31 – 8 * byte...0
|| 0
8 * byte
data ← GPR [rt]
31 – 8 * byte
|| 0
8 * byte
|| 0
32
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