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CHAPTER 2 V
R
4120A
158
Preliminary User’s Manual S15543EJ1V0UM
2.5.4.17 Interrupt exception
(1) Cause
The Interrupt exception occurs when one of the eight interrupt conditions
Note
is asserted. In the V
R
4120A CPU,
interrupt requests from internal peripheral units first enter the ICU and are then notified to the CPU core via one of
four interrupt sources (Int(3:0)) or NMI.
Each of the eight interrupts can be masked by clearing the corresponding bit in the IM field of the Status register,
and all of the eight interrupts can be masked at once by clearing the IE bit of the Status register or setting the
EXL/ERL bit.
Note They are 1 timer interrupt, 5 ordinary interrupts, and 2 software interrupts.
Of the five ordinary interrupts, Int4 is never asserted active in the VR
4120A CPU.
(2) Processing
The common exception vector is used for this exception, and the Int code in the ExcCode field of the Cause
register is set.
The IP field of the Cause register indicates current interrupt requests. It is possible that more than one of the bits
can be simultaneously set (or cleared) if the interrupt request signal is asserted and then deasserted before this
register is read.
The EPC register contains the address of the instruction that caused the exception. However, if this instruction is
in a branch delay slot, the EPC register contains the address of the preceding jump or branch instruction, and the
BD bit of the Cause register is set to 1.
(3) Servicing
If the interrupt is caused by one of the two software-generated exceptions (SW0 or SW1), the interrupt condition is
cleared by setting the corresponding Cause register bit to 0.
If the interrupt is caused by hardware, the interrupt condition is cleared by deactivating the corresponding interrupt
request signal.
2.5.5 Exception processing and servicing flowcharts
The remainder of this chapter contains flowcharts for the following exceptions and guidelines for their handlers:
Common exceptions and a guideline to their exception handler
TLB/XTLB Refill exception and a guideline to their exception handler
Cold Reset, Soft Reset and NMI exceptions, and a guideline to their handler.
Generally speaking, the exceptions are "processed" by hardware (HW); the exceptions are then "serviced" by
software (SW).