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CHAPTER 2 V
R
4120A
Preliminary User’s Manual S15543EJ1V0UM
69
Table 2-4. Load/Store Instruction
Instruction Format and Description
Load Byte LB rt, offset (base)
The offset is sign extended and then added to the contents of the register base to form the virtual
address. The bytes of the memory location specified by the address are sign extended and loaded into
register rt.
Load Byte Unsigned
LBU rt, offset (base)
The offset is sign extended and then added to the contents of the register base to form the virtual
address. The bytes of the memory location specified by the address are zero extended and loaded
into register rt.
Load Halfword LH rt, offset (base)
The offset is sign extended and then added to the contents of the register base to form the virtual
address. The halfword of the memory location specified by the address is sign extended and loaded to
register rt.
Load Halfword
Unsigned
LHU rt, offset (base)
The offset is sign extended and then added to the contents of the register base to form the virtual
address. The halfword of the memory location specified by the address is zero extended and loaded to
register rt.
Load Word LW rt, offset (base)
The offset is sign extended and then added to the contents of the register base to form the virtual
address. The word of the memory location specified by the address is sign extended and loaded to
register rt. In the 64-bit mode, it is further sign extended to 64 bits.
Load Word Left LWL rt, offset (base)
The offset is sign extended and then added to the contents of the register base to form the virtual
address. Shifts to the left the word whose address is specified so that the address-specified byte is at
the left-most position of the word. The result of the shift operation is merged with the contents of
register rt and loaded to register rt. In the 64-bit mode, it is further sign extended to 64 bits.
Load Word Right LWR rt, offset (base)
The offset is sign extended and then added to the contents of the register base to form the virtual
address. Shifts to the right the word whose address is specified so that the address-specified byte is at
the right-most position of the word. The result of the shift operation is merged with the contents of
register rt and loaded to register rt. In the 64-bit mode, it is further sign extended to 64 bits.
Store Byte SB rt, offset (base)
The offset is sign extended and then added to the contents of the register base to form the virtual
address. The least significant byte of register rt is stored to the memory location specified by the
address.
Store Halfword SH rt, offset (base)
The offset is sign extended and then added to the contents of the register base to form the virtual
address. The least significant halfword of register rt is stored to the memory location specified by the
address.
Store Word SW rt, offset (base)
The offset is sign extended and then added to the contents of the register base to form the virtual
address. The lower word of register rt is stored to the memory location specified by the address.
op base rt
offset