Filter
Top Products
CHAPTER 7 PCI CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM
371
7.2 Bus Bridge Functions
7.2.1 Internal bus to PCI transaction
7.2.1.1 Window size
The PCI Controller can have a 2-MB length access window in internal memory space. The V
R
4120A can access
external PCI devices through the access window. The access window can be positioned in the memory range from
1020_0000H to 103F_FFFFH. The base address of the PCI address space is defined by setting of P_PLBA Register.
7.2.1.2 PCI master
The PCI Controller can issue memory commands only. I/O commands, interrupt-acknowledge command, and
special-cycle command are not supported. The PCI Controller can generates Configuration-Cycle in Host-mode.
In the case that Cache-Line-Size register is valid (which means Cache-Line-Size is 4 or 8 or 16 or 32), the PCI
Controller uses 3 kinds of PCI-memory commands for read transactions in accordance with the recommendation in
PCI Specification.
Memory Read: The case of reading a single 32 bit-word.
Memory Read Line: The case of reading more than a 32 bit-word up to the next cache-line boundary.
Memory Read Multiple: The case of reading a block that crosses a cache-line boundary of data.
When Cache-Line-Size register is not valid, the PCI Controller always issues Memory Read Command.
The PCI Controller uses Memory-Write-and-Invalidate commands for write transaction, when all the conditions as
below are satisfied.
- The number of transfer words is just the multiple as the size of cache line.
- “Memory-Write-and-Invalidate” bit in configuration register is set to ‘1’.
- The start address of the write transaction is at a cache boundary.