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CHAPTER 1 INTRODUCTION
26
Preliminary User’s Manual S15543EJ1V0UM
1.5 Block Diagram (Detail)
1.5.1 VR4120A RISC processor core
We will support real-time OS running on high performance RISC processor V
R
4120A core and can perform network
protocols (TCP/IP, PPP, SNMP, HTTP etc) to realize ADSL router and modem. Middleware including RTOS will be
loaded to SDRAM from external PROM and Flash ROM and by setting write protected area for such an area, high
speed processing will be realized together with large size instruction cache.
Features of VR
4120A RISC Processor Core are as follows;
• MIPS/I/II/III instruction set will be supported (FPU, LL, LLD, SC, SCD instruction will be excluded)
• Realize high speed processing of application by supporting high speed multiply and accumulate function
• Includes large size cache memory (Instruction: 16 Kbytes, Data: 8 Kbytes)
• Supports up to 1T byte virtual address space by using full associative TLB
• Implements switching function between Big-Endian and Little-Endian
Figure 1-3. Block Diagram of V
R4120A RISC Processor
V
R
4120A RISC Processor Core
V
R
4120A Data Path
Instruction
Cache
(16 KBytes)
Data
Cache
(8 KBytes)
BUS Controller
SysAD Bus