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APPENDIX A MIPS III INSTRUCTION SET DETAILS
442
Preliminary User’s Manual S15543EJ1V0UM
BC0F
Branch On Coprocessor 0 False
BC0F
BC
0 1 0 0 0
COPz
0 1 0 0 X X
N
ote
BCF
0 0 0 0 0
offset
31 26 25 21 20 16 15 0
655 16
Format:
BC0F offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit
offset
, shifted left two bits and sign-extended. If contents of CP0's condition signal (CpCond), as sampled during
the previous instruction, is false, then the program branches to the target address with a delay of one instruction.
Because the condition line is sampled during the previous instruction, there must be at least one instruction
between this instruction and a coprocessor instruction that changes the condition line.
Operation:
32 T-1:
condition ← not SR
18
T:
target ← (offset
15
)
14
|| offset || 0
2
T+1: if condition then
PC ← PC + target
endif
64 T-1:
condition ← not SR
18
T:
target ← (offset
15
)
46
|| offset || 0
2
T+1: if condition then
PC ← PC + target
endif
Exceptions:
Coprocessor unusable exception
Note See the opcode table below, or A.6 CPU Instruction Opcode Bit Encoding.
Opcode Table:
31
0
30
1
29
0
28
0
27
0
26
0
25
0
24
1
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
0
BC0F
Opcode Coprocessor
number
BC sub-opcode Branch condition