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CHAPTER 2 V
R
4120A
Preliminary User’s Manual S15543EJ1V0UM
155
2.5.4.13 Reserved instruction exception
(1) Cause
The Reserved Instruction exception occurs when an attempt is made to execute one of the following instructions:
• Instruction with an undefined major opcode (bits 31 to 26)
• SPECIAL instruction with an undefined minor opcode (bits 5 to 0)
• REGIMM instruction with an undefined minor opcode (bits 20 to 16)
• 64-bit instructions in 32-bit User or Supervisor mode
• RR instruction with an undefined minor op code (bits 4 to 0)
64-bit operations are always valid in Kernel mode regardless of the value of the KX bit in the Status register. This
exception is not maskable.
(2) Processing
The common exception vector is used for this exception, and the RI code in the ExcCode field of the Cause
register is set.
The EPC register contains the address of the instruction that caused the exception. However, if this instruction is
in a branch delay slot, the EPC register contains the address of the preceding jump or branch instruction, and the
BD bit of the Cause register is set to 1.
(3) Servicing
All currently defined MIPS ISA instructions can be executed. The process executing at the time of this exception
is handled by a UNIX SIGILL/ILL_RESOP_FAULT (illegal instruction/reserved operand fault) signal. This error is
usually fatal.