Filter
Top Products
CHAPTER 7 PCI CONTROLLER
388
Preliminary User’s Manual S15543EJ1V0UM
Figure 7-14. An Example How to Connect AD [31:16] Signal Line to IDSEL Port
AD[x]
AD[31:0]
IDSEL
PCI device
Figure 7-15. Address Stepping for IDSEL
Clock
FRAME#
AD
IDSEL
IRDY#
TRDY#
DEVSEL#
Address Data
7.4.2 PCI bus arbiter
The PCI Controller has an arbiter that supports 4 external PCI master devices. This arbiter is enabled only when in
Host mode and PARBEN is set to high. When this internal arbiter is disabled, the PCI Controller asserts REQ_B
output signal to external arbiter in order to acquire PCI bus both in NIC and in Host mode.
When there are less than 4 PCI master devices on PCI bus and this arbiter is used, REQ_B pins that are not used
should be pull-up.
This internal arbiter has 2 modes for arbitration algorithm. These modes can be selected by PARBM bit in
P_HMCR register.
7.4.2.1 Alternating mode
PCI master devices except the PCI Controller are arbitrated as one group in this mode. Priority alternates The PCI
Controller with the group of PCI master devices on the transaction by transaction. In the group of PCI master devices,
priority rotates among them.
When all REQ_B input signals to this arbiter go up to high, which means no device issues the acquisition of PCI
bus, this arbiter gives the right of use of PCI bus to the PCI Controller in order to make the PCI Controller drive AD
lines and CBE_B lines as arbitration parking.