APPENDIX A MIPS III INSTRUCTION SET DETAILS
462
Preliminary User’s Manual S15543EJ1V0UM
BNE
Branch On Not Equal
BNE
rs
BNE
0 0 0 1 0 1
rt offset
31 26 25 21 20 16 15 0
655 16
Format:
BNE rs, rt, offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit
offset,
shifted left two bits and sign-extended. The contents of general register
rs
and the contents of general
register
rt
are compared. If the two registers are not equal, then the program branches to the target address, with
a delay of one instruction.
Operation:
32 T:
target ← (offset
15
)
14
|| offset || 0
2
condition ← (GPR [rs] ≠ GPR [rt])
T+1: if condition then
PC ← PC + target
endif
64 T:
target ← (offset15
)
46
|| offset || 0
2
condition ← (GPR [rs] ≠ GPR [rt])
T+1: if condition then
PC ← PC + target
endif
Exceptions:
None