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APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM
589
Figure A-1. VR4120AOpcode Bit Encoding (2/2)
23...21
COP0 rs
25, 2401234567
0MFDMFεγ γ MT DMTεγ γ
1BC γγγγγγγ
2CO
3
18...16
COP0 rt
20...19 01234567
0 BCF BCT BCFL BCTL γγγγ
1 γγγγγγγγ
2 γγγγγγγγ
3 γγγγγγγγ
2...0
CP0 Function
5...3 01234567
0 φ TLBR TLBWI φφφTLBWR φ
1TLBP φφφφφφφ
2 ξφφφφφφφ
3ERET χφφφφφφφ
4 φ STANDBY SUSPEND HIBERNAT φφφφ
5 φφφφφφφφ
6 φφφφφφφφ
7 φφφφφφφφ
Key:
* Operation codes marked with an asterisk cause reserved instruction exceptions in all current
implementations and are reserved for future versions of the architecture.
γ Operation codes marked with a gamma cause a reserved instruction exception. They are reserved for future
versions of the architecture.
δ Operation codes marked with a delta are valid only for V
R
4400 Series processors with CP0 enabled, and
cause a reserved instruction exception on other processors.
φ Operation codes marked with a phi are invalid but do not cause reserved instruction exceptions in V
R
4121
implementations.
ξ Operation codes marked with a xi cause a reserved instruction exception on VR
4121 processor.
χ Operation codes marked with a chi are valid on V
R
4000 Series only.
ε Operation codes marked with epsilon are valid when the processor operating as a 64-bit processor. These
instructions will cause a reserved instruction exception if 64-bit operation is not enabled.
π Operation codes marked with a pi are invalid and cause coprocessor unusable exception.
θ Operation codes marked with a theta are valid when MIPS16 instruction execution is enabled, and cause a
reserved instruction exception when MIPS16 instruction execution is disabled.