CHAPTER 1 INTRODUCTION
56
Preliminary User’s Manual S15543EJ1V0UM
1.12 Clock Control Unit
This section describe
µ
PD98502’s internal clock is supplied by Clock Control Unit (CCU) with following figure.
Figure 1-13. Block Diagram of Clock Control Unit
UART
25/16.7
MHz
PLL
(x6)
1/2
1/3
CCU (CLOCK CONTROL UNIT)
ATM Cell
Processor
33/25/16.5 MHz
66 MHz
USB
Controller
48 MHz
USBCLK (12 MHz)
Peripheral
100/66 MHz
System
Controller
macstop
usbstop
atmstop
1/3
SCLK (33 MHz)
100/66MHz
66 MHz
Ethernet
Controller
#1
25 MHz
25 MHz
MIRCLK (25 MHz)
MITCLK (25 MHz)
66 MHz
66 MHz
Ethernet
Controller
#2
25 MHz
25 MHz
MIRCLK (25 MHz)
MITCLK (25 MHz)
66 MHz
PCI
Controller
PCICLK (33 MHz)
66 MHz
IBUS
pcistop
mac2stop
CLOCK
ENABLER
CLOCK
ENABLER
CLOCK
ENABLER
CLOCK
ENABLER
CLOCK
ENABLER
1/2
1/4
1/8
66 MHz
SEL
V
R
4120A
URTCLK
(18.432 MHz)