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CHAPTER 7 PCI CONTROLLER
398
Preliminary User’s Manual S15543EJ1V0UM
7.5.12 P_HMCR (Host Mode Control Register)
This register is used to control the PCI-Host functions.
R/WBits Field
Internal
bus
PCI
Default Description
31 PRSTO R/W R 0 Reset Out.
PCI reset output as Host.
The PCI Controller asserts PRSTO during this bit is ‘1’.
30:1 Reserved - - 0 Hardwired to ‘0’s.
0 PARBM R/W R/W 0 PCI arbiter mode.
The bit defines arbiter mode.
0: Alternating mode
1: Rotating mode
7.5.13 P_PCDR (Power Consumption Data Register)
This register is used to indicate the power consumption data for each power state.
The V
R
4120A should be set the value to this register as initialization. The unit of data is “0.01Watts”.
R/WBits Field
Internal
bus
PCI
Default Description
31:24 D3CSP R/W R 00H D3 Power Consumption Data.
23:16 Reserved - - 00H Hardwired to ‘00H’.
15:8 D1CSP R/W R 00H D1 Power Consumption Data.
7:0 D0CSP R/W R 00H D0 Power Consumption Data.
7.5.14 P_PDDR (Power Dissipation Data Register)
This register is used to indicate the power dissipation data for each power state.
The V
R
4120A should be set the values to this register as initialization. The unit of data is “0.01Watts”.
R/WBits Field
Internal
bus
PCI
Default Description
31:24 D3DSP R/W R 00H D3 Power Dissipation Data.
23:16 Reserved - - 00H Hardwired to ‘00H’.
15:8 D1DSP R/W R 00H D1 Power Dissipation Data.
7:0 D0DSP R/W R 00H D0 Power Dissipation Data.