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CHAPTER 2 V
R
4120A
Preliminary User’s Manual S15543EJ1V0UM
117
2.4.4 System control coprocessor
The System Control Coprocessor (CP0) is implemented as an integral part of the CPU, and supports memory
management, address translation, exception processing, and other privileged operations. The CP0 contains the
registers and a 32-entry TLB shown in Figure 2-32. The sections that follow describe how the processor uses each of
the memory management-related registers.
Remark Each CP0 register has a unique number that identifies it; this number is referred to as the register
number.
Figure 2-32. CP0 Registers and TLB
31
0
Remark
TLB
(Safe entries)
(See Random register for
TLB Wired boundary.)
127/255
EntryHi
10*
EntryLo0
2*
Index
0*
Context
4*
BadVAddr
8*
Compare
11*
Count
9*
Random
1*
EntryLo1
3*
PageMask
5*
Status
12*
Cause
13*
WatchLo
18*
EPC
14*
Wired
6*
PRId
15*
WatchHi
19*
XContext
20*
ErrorEPC
30*
Cache Error
27*
Parity Error
26*
LLAddr
17*
TagLo
28*
TagHi
29*
Config
16*
*: Register number
Used for memory management system
Used for exception processing