APPENDIX A MIPS III INSTRUCTION SET DETAILS
448
Preliminary User’s Manual S15543EJ1V0UM
BEQ
Branch On Equal
BEQ
rs
BEQ
0 0 0 1 0 0
rt offset
31 26 25 21 20 16 15 0
655 16
Format:
BEQ rs, rt, offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit
offset
, shifted left two bits and sign-extended. The contents of general register
rs
and the contents of general
register
rt
are compared. If the two registers are equal, then the program branches to the target address, with a
delay of one instruction.
Operation:
32 T:
target ← (offset
15
)
14
|| offset || 0
2
condition ← (GPR [rs] = GPR [rt])
T+1: if condition then
PC ← PC + target
endif
64 T:
target ← (offset
15
)
46
|| offset || 0
2
condition ← (GPR [rs] = GPR [rt])
T+1: if condition then
PC ← PC + target
endif
Exceptions:
None