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APPENDIX A MIPS III INSTRUCTION SET DETAILS
546
Preliminary User’s Manual S15543EJ1V0UM
SH
Store Halfword
SH
base
SH
1 0 1 0 0 1
rt offset
31 26 25 21 20 16 15 0
655 16
Format:
SH rt, offset (base)
Description:
The 16-bit
offset
is sign-extended and added to the contents of general register
base
to form an unsigned effective
address. The least-significant halfword of register
rt
is stored at the effective address. If the least-significant bit of
the effective address is non-zero, an address error exception occurs.
Operation:
32 T:
vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR [base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ←
pAddr
PSIZE - 1...3
|| (pAddr
2...0
xor (ReverseEndian
2
|| 0))
byte ← vAddr
2...0
xor (BigEndianCPU
2
|| 0)
data ← GPR [rt]63 – 8 * byte...0
|| 0
8 * byte
StoreMemory (uncached, HALFWORD, data, pAddr, vAddr, DATA)
64 T:
vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR [base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE - 1...3
|| (pAddr
2...0
xor (ReverseEndian
2
|| 0))
byte ← vAddr
2...0
xor (BigEndianCPU
2
|| 0)
data ← GPR [rt]63 – 8 * byte...0
|| 0
8 * byte
StoreMemory (uncached, HALFWORD, data, pAddr, vAddr, DATA)
Exceptions:
TLB refill exception
TLB invalid exception
TLB modification exception
Bus error exception
Address error exception