CHAPTER 1 INTRODUCTION
Preliminary User’s Manual S15543EJ1V0UM
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1.11 Interrupts
The controller supports maskable interrupts and Non-Maskable to the CPU.
Figure 1-12. Interrupt Signal Connection
USB Controller
Ethernet Controller #1
ATM Cell Processor
System Controller
V
R
4120A
S_ISR
intb[0]
intb[1]
intb[2]
intb[4]
intb[3]
EXTNMI
EXTINT
nmib
S_IMR
BUS-IF
UART
TIMER
Ethernet Controller #2
S_NSR
S_NER
DSU
BUS-IF
PCI Controller