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CHAPTER 5 ETHERNET CONTROLLER
288
Preliminary User’s Manual S15543EJ1V0UM
5.2.11 En_PTVR (Pause Timer Value Read Register)
Bits Field R/W Default Description
31:16 Reserved R 0 Reserved for future use.
15:0 PTCT R 0 Pause timer counter:
This field indicates the current pause timer value.
5.2.12 En_VLTP (VLAN Type Register)
Bits Field R/W Default Description
31:16 Reserved R/W 0 Reserved for future use. Write 0s.
15:0 VLTP R/W 0 VLAN type:
This field sets ETPID value.
Receive:
MAC Control Block detects a VLAN frame by comparing this field
with the ETPID field in a received packet.
Transmit:
If APD bit in En_MACC2 register is set to a ‘1’ and the ETPID field
in the current transmit packet is equal to the value in this field, MAC pads as
a VLAN packet when the current packet should be padded.
5.2.13 En_MIIC (MII Configuration Register)
Bits Field R/W Default Description
31:16 Reserved R/W 0 Reserved for future use. Write 0s.
15 MIRST R/W 0 MII Management Interface Block software reset:
Setting this bit to a ‘1’ forces the MII Management Interface Block to transit to
a software reset operation. In order to complete the software reset, this bit
needs to be cleared.
14:4 Reserved R/W 0 Reserved for future use. Write 0s.
3:2 CLKS R/W 0 Select frequency range:
This field sets the frequency range of the internal clock.
MDC is generated by dividing down the internal clock and the clock division
is set by these bits. The settings of these bits are:
00: the internal clock is equal to 25 MHz
01: the internal clock is less than or equal to 33 MHz
10: the internal clock is less than or equal to 50 MHz
11: the internal clock is less than or equal to 66 MHz (normal case)
MDC is set less than or equal to 2.5MHz. by the setting of this bits.
1:0 Reserved R/W 0 Reserved for future use. Write 0s.
5.2.14 En_MCMD (MII Command Register)
Bits Field R/W Default Description
31:2 Reserved W 0 Reserved for future use. Write 0s.
1 SCANC W 0 SCAN command:
When this bit is set to a ‘1’, MAC Control Block executes the SCAN
command.
0 RSTAT W 0 MII management read:
When this bit is set to a ‘1’, MAC Control Block executes the read access
through MII management interface.