Filter
Top Products
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM
481
DMTC0
Doubleword Move To System Control Coprocessor
DMTC0
DMT
0 0 1 0 1
COP0
0 1 0 0 0 0
rt rd
31 26 25 21 20 16 15 0
6 555
0
0 0 0 0 0 0 0 0 0 0 0
11 10
11
Format:
DMTC0 rt, rd
Description:
The contents of general register
rt
are loaded into coprocessor register
rd
of the CP0.
This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or
supervisor mode causes a reserved instruction exception.
All 64-bits of the coprocessor 0 register are written from the general register source. The operation of DMTC0 on a
32-bit coprocessor 0 register is undefined.
Because the state of the virtual address translation system may be altered by this instruction, the operation of load
instructions, store instructions, and TLB operations immediately prior to and after this instruction are undefined.
Operation:
64 T:
data ← GPR [rt]
T+1:
CPR [0, rd] ← data
Exceptions:
Coprocessor unusable exception (In 64-bit/32-bit user and supervisor mode if CP0 not enabled)
Reserved instruction exception (32-bit user mode/supervisor mode)