APPENDIX A MIPS III INSTRUCTION SET DETAILS
554
Preliminary User’s Manual S15543EJ1V0UM
SRAV
Shift Right Arithmetic Variable
SRAV
rs
SPECIAL
0 0 0 0 0 0
rt rd
0
0 0 0 0 0
SRAV
0 0 0 1 1 1
31 26 25 21 20 16 15 11 10 6 5 0
655556
Format:
SRAV rd, rt, rs
Description:
The contents of general register
rt
are shifted right by the number of bits specified by the low-order five bits of
general register
rs
, sign-extending the high-order bits.
The result is placed in register
rd
.
In 64-bit mode, the operand must be a valid sign-extended, 32-bit value.
Operation:
32 T:
s
←
GPR [rs]
4...0
GPR [rd]
←
(GPR [rt]
31
)
s
|| GPR [rt]
31...s
64 T:
s
←
GPR [rs]
4...0
temp
←
(GPR [rt]
31
)
s
|| GPR [rt]
31...s
GPR [rd]
←
(temp
31
)
32
|| temp
Exceptions:
None