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APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM
499
JALR
Jump And Link Register
JALR
rs
SPECIAL
0 0 0 0 0 0
0
0 0 0 0 0
rd
0
0 0 0 0 0
JALR
0 0 1 0 0 1
31 26 25 21 20 16 15 11 10 6 5 0
6 5555 6
Format:
JALR rs
JALR rd, rs
Description:
The program unconditionally jumps to the address contained in general register
rs
, with a delay of one instruction.
When a MIPS16 instruction can be executed, the program unconditionally jumps with a delay of one instruction to
the address indicated by the value of clearing the least significant bit of the general-purpose register
rs
to 0. Then,
the content of the least significant bit of the general-purpose register
rs
is set to the ISA mode bit (internal). The
address of the instruction after the delay slot is placed in general register
rd
. The default value of
rd
, if omitted in
the assembly language instruction, is 31. When a MIPS16 instruction can be executed, the value of bit 0 of
rd
indicates the ISA mode bit before jump. Register specifiers
rs
and
rd
may not be equal, because such an
instruction does not have the same effect when re-executed. Because storing a link address destroys the contents
of
rs
if they are equal. However, an attempt to execute this instruction is
not
trapped, and the result of executing
such an instruction is undefined.
Since 32-bit length instructions must be word-aligned, a JALR instruction must specify a target register (
rs
) that
contains an address whose two low-order bits are zero when a MIPS16 instruction can be executed. If these low-
order bits are not zero, an address error exception will occur when the jump target instruction is subsequently
fetched.
Operation:
32, 64 T:
temp ← GPR [rs]
GPR [rd] ← (PC + 8)
63..1
|| ISA MODE
If MIPS16EN = 1 then
else
GPR [rd] ← PC + 8
endif
T+1:
PC ← temp
63..1
|| 0
If MIPS16EN = 1 then
else
PC ← temp
endif
ISA MODE ← temp
0
Exceptions:
None