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CHAPTER 2 V
R
4120A
140
Preliminary User’s Manual S15543EJ1V0UM
2.5.3.9 XContext register (20)
The read/write XContext register contains a pointer to an entry in the page table entry (PTE) array, an operating
system data structure that stores virtual-to-physical address translations. If a TLB miss occurs, the operating system
loads the untranslated data from the PTE into the TLB to handle the software error.
The XContext register is used by the XTLB Refill exception handler to load TLB entries in 64-bit addressing mode.
The XContext register duplicates some of the information provided in the BadVAddr register, and puts it in a form
useful for the XTLB exception handler.
This register is included solely for operating system use. The operating system sets the PTEBase field in the
register, as needed. Figure 2-57 shows the format of the XContext register.
Figure 2-57. XContext Register Format
32
42 2929
035 34 3363 4 3
PTEBase R BadVPN2 0
PTEBase : The PTEBase field is a base address of the PTE entry table.
R : Space type (00 → User, 01→ Supervisor, 11 → Kernel). The setting of this field matches virtual
address bits 63 and 62.
BadVPN2 : This field holds the value (VPN2) obtained by halving the virtual page number of the most recent
virtual address for which translation failed.
0 : RFU. Write 0 in a write operation. When this field is read, 0 is read.
The 29-bit BadVPN2 field has bits 39 to 11 of the virtual address that caused the TLB miss; bit 10 is excluded
because a single TLB entry maps to an even-odd page pair. For a 1-Kbyte page size, this format may be used
directly to address the pair-table of 8-byte PTEs. For 4-Kbyte or more page and PTE sizes, shifting or masking this
value produces the appropriate address.
2.5.3.10 Parity error register (26)
The Parity Error (PErr) register is a readable/writeable register. This register is defined to maintain software-
compatibility with the V
R
4100, and is not used in hardware because the V
R
4120A CPU has no parity.
Figure 2-58 shows the format of the PErr register.
Figure 2-58. Parity Error Register Format
824
031 8 7
0 Diagnostic
Diagnostic : 8-bit self diagnostic field.
0 : RFU. Write 0 in a write operation. When this field is read, 0 is read.