APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM
555
SRL
Shift Right Logical
SRL
0
0 0 0 0 0
SPECIAL
0 0 0 0 0 0
rt rd sa
SRL
0 0 0 0 1 0
31 26 25 21 20 16 15 11 10 6 5 0
6 5555 6
Format:
SRL rd, rt, sa
Description:
The contents of general register
rt
are shifted right by
sa
bits, inserting zeros into the high-order bits.
The result is placed in register
rd
.
In 64-bit mode, the operand must be a valid sign-extended, 32-bit value.
Operation:
32 T:
GPR [rd]
←
0
sa
|| GPR [rt]
31...sa
64 T:
s
←
0 || sa
temp
←
0
s
|| GPR [rt]
31...s
GPR [rd]
←
(temp
31
)
32
|| temp
Exceptions:
None