APPENDIX A MIPS III INSTRUCTION SET DETAILS
458
Preliminary User’s Manual S15543EJ1V0UM
BLTZ
Branch On Less Than Zero
BLTZ
rs
REGIMM
0 0 0 0 0 1
BLTZ
0 0 0 0 0
offset
31 26 25 21 20 16 15 0
655 16
Format:
BLTZ rs, offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit
offset
, shifted left two bits and sign-extended. If the contents of general register
rs
are smaller than zero, then the
program branches to the target address, with a delay of one instruction.
Operation:
32 T:
target ← (offset
15
)
14
|| offset || 0
2
condition ←
(
GPR
[
rs
]
31
= 1
)
T+1: if condition then
PC ← PC + target
endif
64 T:
target ← (offset15
)
46
|| offset || 0
2
condition ←
(
GPR
[
rs
]
63
= 1
)
T+1: if condition then
PC ← PC + target
endif
Exceptions:
None