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APPENDIX A MIPS III INSTRUCTION SET DETAILS
562
Preliminary User’s Manual S15543EJ1V0UM
SWL
Store Word Left (1/3)
SWL
base
SWL
1 0 1 0 1 0
rt offset
31 26 25 21 20 16 15 0
655 16
Format:
SWL rt, offset (base)
Description:
This instruction can be used with the SWR instruction to store the contents of a register into four consecutive bytes
of memory, when the bytes cross a word boundary. SWL stores the register into the appropriate part of the high-
order word of memory; SWR stores the register into the appropriate part of the low-order word.
The SWL instruction adds its sign-extended 16-bit
offset
to the contents of general register
base
to form a virtual
address that may specify an arbitrary byte. It alters only the word in memory that contains that byte. From one to
four bytes will be stored, depending on the starting byte specified.
Conceptually, it starts at the most-significant byte of the register and copies it to the specified byte in memory; then
it copies bytes from register to memory until it reaches the low-order byte of the word in memory.
No address error exceptions due to alignment are possible.
address 4
address 0
memory
7 6 5 4
3 2 1 0
before
after
$24
register
SWL $24, 4 ($0)
A B C D
address 4
address 0
7 6 5 A
3 2 1 0