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Preliminary User’s Manual S15543EJ1V0UM
2.4.4.1 Format of a TLB entry
Figure 2-33 shows the TLB entry formats for both 32- and 64-bit modes. Each field of an entry has a corresponding
field in the EntryHi, EntryLo0, EntryLo1, or PageMask registers.
Figure 2-33. Format of a TLB Entry
114115 96127 107 106
(a) 32-bit mode
0 MASK 0
82121
13 8 11
6495 75 74 73 72 71
VPN2 G 0 ASID
5960
224
3263 3738 35 34 33
0
PFN C D V 0
13 1 1
2728
224
031 56 3 2 1
0
PFN C D V 0
13 1 1
210211 192255 203 202
(b) 64-bit mode
0 MASK 0
190 189
8212
22
29
45
8 11
128
191
139 138 137
136
135
R 0 VPN2
G
0
ASID
9192
2236
64127 6970 67 66 65
0 PFN C D V 0
13 1
1
2728
2236
0
63 56 3
2
1
0 PFN C D V 0
13 1 1
167168
The format of the EntryHi, EntryLo0, EntryLo1, and PageMask registers are nearly the same as the TLB entry.
However, it is unknown what bit of the EntryHi register corresponds to the TLB G bit.