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APPENDIX A MIPS III INSTRUCTION SET DETAILS
512
Preliminary User’s Manual S15543EJ1V0UM
LHU
Load Halfword Unsigned
LHU
base
LHU
1 0 0 1 0 1
rt offset
31 26 25 21 20 16 15 0
655 16
Format:
LHU rt, offset (base)
Description:
The 16-bit
offset
is sign-extended and added to the contents of general register
base
to form a virtual address.
The contents of the halfword at the memory location specified by the effective address are zero-extended and
loaded into general register
rt
.
If the least-significant bit of the effective address is non-zero, an address error exception occurs.
Operation:
32 T:
vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR [base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ←
pAddr
PSIZE - 1...3
|| (pAddr
2...0
xor (ReverseEndian
2
|| 0))
mem ← LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA)
byte ← vAddr
2...0
xor (BigEndianCPU
2
|| 0)
GPR
[
rt
]
← 0
16
|| mem
15 + 8 * byte...8 * byte
64 T:
vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR [base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE - 1...3
|| (pAddr
2...0
xor (ReverseEndian
2
|| 0))
mem ← LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA)
byte ← vAddr
2...0
xor (BigEndianCPU
2
|| 0)
GPR [rt] ← 0
48
|| mem
15 + 8 * byte...8 * byte
Exceptions:
TLB refill exception
TLB invalid exception
Bus Error exception
Address error exception