APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM
567
SWR
Store Word Right (3/3)
SWR
Given a doubleword in a register and a doubleword in memory, the operation of SWR instruction is as follows:
B C D E F GA H
J K L M N OI P
Register
Memory
SWR
vAddr2..
0
Destination Type Offset
(LEM)
0
1
2
3
4
5
6
7
IJKLEFGH
IJKLFGHP
IJKLGHOP
I JKLHNOP
E FGHMNOP
FGHLMNOP
GHKLMNOP
HJKLMNOP
3
2
1
0
3
2
1
0
0
1
2
3
4
5
6
7
Remark
LEM
Little-endian memory (BigEndianMem = 0)
Type
AccessType (see Table 2-3. Byte Specification Related to Load and Store Instructions)
sent to memory
Offset
pAddr2..0 sent to memory
Exceptions:
TLB refill exception
TLB invalid exception
TLB modification exception
Bus error exception
Address error exception