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116 AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
28 II_NS Instruction Pipeline (IP) Empty Mode.
0: IM Interface may make requests to Instruction Memory (IM) when the IP is not empty.
(Default)
1: IM Interface only makes requests to IM after the IP is empty.
Note: Enabling this mode reduces performance.
27:25 RSVD Reserved.
24 CC_SER COF Cache Serialization.
0: Allow more than one outstanding request in COF cache. (Default)
1: Allow only one request in the COF cache.
Note: Enabling COF cache serialization may reduce performance.
23:21 RSVD Reserved.
20 RQ_SER Request Queue Serialization.
0: Allow more than one request in the Request Queue. (Default)
1: Only one request is allowed in the Request Queue.
Note: Enabling RQ serialization reduces performance.
19:17 RSVD Reserved.
16 II_SER Instruction Memory Request Serialization.
0: IM requests are not serialized. (Default)
1: IM Interface waits until IM responds to a request before IM Interface issues the next
request.
Note: Enabling IM Interface serialization reduces performance.
15 RSVD Reserved.
14 II_IMFLSH Instruction Memory Flush.
0: IF never issues flush requests to IM.
1: IF may issue flush requests to IM. (Default)
Note: Enabling IM flushing usually increases performance.
13 RSVD Reserved.
12 CC_L0 Level-0 COF Cache.
0: Disable.
1: Enable. (Default)
Note: Enabling the L0 COF cache increases performance. Unless CC_L1 is enabled
(bit 0 = 1), then CC_L0 has no effect.
11 RSVD Reserved.
10 DMM_DIS Debug Management Mode (DMM).
0: The COF cache and return stack is neither used nor updated during DMM. (Default)
1: The COF cache and return stack may be used and updated during DMM.
Note: Disabling the COF cache and return stack during DMM may reduce performance
but make debug easier.
9 RSVD Reserved.
8 CC_PS Power Saving Mode.
0: Disable. (Default)
1: Enable.
Note: CC_L1 must be disabled (bit 0 = 0) to enable power saving.
7 RSVD Reserved.
IF_CONFIG_MSR Bit Descriptions (Continued)
Bit Name Description