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222 AMD Geode™ LX Processors Data Book
GeodeLink™ Memory Controller Register Descriptions
33234H
6.2.1.5 GLD Power Management (GLD_MSR_PM)
6.2.1.6 GLD Diagnostic (GLD_MSR_DIAG)
This register is reserved for internal use by AMD and should not be written to.
MSR Address 20002004h
Typ e R /W
Reset Value 00000000_00000000h
GLD_MSR_PM Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
PM1
RSVD
PM0
GLD_MSR_PM Bit Descriptions
Bit Name Description
63:32 RSVD (RO) Reserved (Read Only). Reads back 0s.
31:3 RSVD Reserved.
2PM1 Power Mode 1. Clock gating for clock domains 0 (GLIU clock) and 1 (GLMC clock). Once
the GLMC becomes idle, it enters PMode1 by 1) closing all banks with a ‘precharge all’
command to the DIMMs, 2) issuing a self-refresh command, 3) bringing CKE1 and CKE0
(balls F4 and E4 respectively) low and putting the address and control pins in TRI_STATE
mode, and 4) shutting off its GLIU and GLMC clocks on the next clock after the self-
refresh. The GLMC resumes to full power after any activity is detected (i.e., a GLIU
request after reset).
0: Disable clock gating. Clocks are always ON. (Default)
1: Enable active hardware clock gating.
1 RSVD Reserved.
0PM0 Power Mode 0. Clock gating for clock domain 0 (GLIU clock). Once the GLMC becomes
idle, it enters PMode0 by shutting off its GLIU clock on the next cycle. Its GLMC clock
remains on to maintain the refresh counters, as do the SDRAM clocks. The GLMC
resumes full power either after any activity is detected, or when it needs to perform a
refresh.
0: Disable clock gating. Clocks are always ON. (Default)
1: Enable active hardware clock gating.
MSR Address 20002005h
Typ e R /W
Reset Value 00000000_00000000h