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AMD Geode™ LX Processors Data Book 431
Video Processor Register Descriptions
33234H
6.8.3.12 CRT Clock Select (CCS)
This register is made up of read only reserved bits and spare bits with no functions.
6.8.3.13 Video Y Scale (VYS)
6.8.3.14 Video X Scale (VXS)
VP Memory Offset 058h
Typ e R /W
Reset Value 00000000_00000000h
VP Memory Offset 060h
Typ e R /W
Reset Value 00000000_00000000h
VYS Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
Y_ACC_INIT VID_Y_SCL
VYS Bit Descriptions
Bit Name Description
63:32 RSVD (RO) Reserved (Read Only). Reads back as 0.
31:20 Y_ACC_INIT Y Accumulator Initial Value. Load this value before each video frame. Works with verti-
cal scaling, in case a sub-line offset is required prior to displaying video. Pad 4 LSBs with
0 when loading.
19:0 VID_Y_SCL Video Y Scale Factor. Bits [19:16] represent the integer part of vertical scale factor of
the video window according to the following formula:
Y_SCL_INT = 1/Ys
Where:
Ys = Arbitrary vertical scaling factor.
Bits [15:0] represent the fractional part of vertical scale factor of the video window
according to the following formula:
VID_Y_SCL = FFFFh * 1/Ys
Note: If no scaling is intended, set to 10000h. Will be greater than 10000h when down-
scaling. Will be less than 10000h when upscaling.
VP Memory Offset 068h
Typ e R /W
Reset Value 00000000_00000000h
VXS Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
X_ACC_INIT VID_X_SCL