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AMD Geode™ LX Processors Data Book 581
GeodeLink™ PCI Bridge Register Descriptions
33234H
6.16.2.2 GLPCI Arbiter Control (GLPCI_ARB)
9LDE Latency Disconnect Enable. Writing 1, causes the PCI interface to disconnect from a
PCI bus master when a latency timer expiration occurs. This enforces the configured min-
imum latency upon PCI bus masters where the GLPCI module is a target on the PCI bus.
The latency timer must be greater than 0 when using this feature.
8RUPO Relax Up-Stream Ordering. Removes ordering restrictions for out-bound read response
data with respect to in-bound write data. Setting this bit also causes the GLPCI to clear
the SEND_RESPONSE flag for in-bound GLIU request packets. This bit should be
cleared for normal operation.
7BZ Bizarro Flag. BIZARRO flag configuration to use on in-bound I/O reads and writes.
6NI No Invalidate Flag. Force the INVALIDATE flag to be cleared for all in-bound writes.
5ISO In-Bound Strong Ordering. Disables the ability of in-bound reads to coherently pass
posted in-bound writes. When set to 1, a PCI read request received by the host bridge
target is not forwarded to GLIU until all posted write data has been flushed to memory.
This bit should be cleared for normal operation.
4OWC Out-Bound Write Combining. Enables concatenation of out-bound write bursts into a
larger PCI burst. Setting this bit does NOT add any additional latency to out-bound writes.
3IWC In-Bound Write Combining. Enables combining of different in-bound PCI write transac-
tions into a single GLIU host write transaction. When cleared to 0, PCI write data
received from the host bridge target is not held in the posted write buffer; a GLIU transac-
tion is generated immediately.
2PCD In-Bound PCI Configuration Disable. Disables the handling of in-bound PCI configura-
tion cycles. When set to 1, PCI configuration cycles are not accepted by this PCI inter-
face. After reset, the GLPCI module accepts in-bound PCI configuration cycles to provide
a means of generating MSR transactions onto the internal GLIU. For normal operation
this capability should be disabled.
1IE I/O Enable. Enable handling of in-bound I/O transactions from PCI. When set to 1, the
PCI interface accepts all in-bound I/O transactions from PCI. This mode is only intended
for design verification purposes. When cleared to 0, no in-bound I/O transactions are
accepted.
0ME Memory Enable. Enable handling of in-bound memory access transaction from PCI.
When cleared to 0 the PCI interface does not accept any in-bound memory transactions
from the PCI bus. When set to 1, the PCI interface accepts in-bound memory transac-
tions for those address ranges defined in the region configuration registers.
MSR Address 50002011h
Typ e R /W
Reset Value 00000000_00000000h
GLPCI_CTRL Bit Descriptions (Continued)
Bit Name Description
GLPCI_ARB Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
CR R2 R1 R0 CH H2 H1 H0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
COV
OV2
OV1
OV0
RSVD
MSK2
MSK1
MSK0
RSVD
CPRE
PRE2
PRE1
PRE0
BM1
BM0
RSVD
EA
BMD
PARK