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218 AMD Geode™ LX Processors Data Book
GeodeLink™ Memory Controller
33234H
6.1.2 Power Control
The GLMC employs some methods of power control for
power savings. One method is that it TRI-STATEs the
GLMC address and control pins when there is no valid
address or control data being driven (i.e., when all the chip
selects are inactive (high). This feature is enabled via
GLMC MSR 2000001Dh[12] (TRI_STATE_DIS), and is dis-
abled by default.
The second and third methods of power control are
effected via the GLMC’s GLD_MSR_PM register (MSR
20002004h). The two modes of power control achievable
via this register are PMode0 and PMode1. If PMode0 is
enabled, whenever the GLMC’s internal state machines
are idle and no requests or data are being processed, the
GLMC will shut off one of its two clocks, mb_clk, to save
power. Its other clock, mc_clk, remains active to maintain
the refresh counters. If it needs to perform a refresh, or if a
GLIU request comes into the GLMC, mb_clock is reacti-
vated on the next cycle and the GLMC resumes full power.
If PMode1 is enabled, the GLMC goes into a deeper level
of power-down when it becomes idle. It first sets up the
DRAM to go into self-refresh, then shuts off both of its
clocks. A wakeup signal in the form of a GLIU request (or
reset if the system powers down completely) gets the
GLMC back into full power. Per DRAM requirements, the
GLMC waits 200 mc_clocks before accepting the next
GLIU request (see GLMC MSR 2000001Ah[15:8]). Also, in
order to avoid going into PMode0 or PMode1 unnecessar-
ily, there are programmable sensitivity counters for both
modes (see GLMC MSR 20000020h) that provide a way to
filter out idle periods less than the duration specified in
these counters.
Sequence of steps that occur on entry into PMode1 (i.e.,
Save-to-RAM):
6.1.2.1 Entry into PMode1 (Save-to-RAM)
When Save-to-RAM is requested:
1) ACPI software performs all required memory writes.
2) If necessary, write a non-zero value to PM1_SENS
counter (MSR 200000020h[63:32]). This filters out
GLMC idle periods less than counter value, so
PMode1/Save-to-RAM is only entered on sufficiently
long idle periods.
3) Set PMode1 in MSR 20002004h[2] to 1 to enable
PMode1. On the next GLMC idle condition that is
longer than the value in PM1_SENS, the GLMC per-
forms the following:
4) Finish any outstanding memory transactions if any.
5) Issue self-refresh command to put DIMMs in self-
refresh. This entails issuing a refresh command with
CKE = 0.
6) Turn off both GLMC’s internal mc_clk and mb_clk.
6.1.2.2 Resume from PMode1
Either a reset or a GLIU request wakes up the GLMC from
PMode1, triggering the following sequence:
1) Both internal clocks, mb_clk and mc_clk, resume on
next clock after wakeup event.
2) CKE is released on next clock after clocks resume. If
power was removed during entry into PMode1, CKE is
released as in a cold boot sequence.
3) A Mode Register Set cycle to the DRAM is generated
using the data that was programmed into the
MC_CF07_DATA register (MSR 20000018h)
4) After 200 SDCLKs (as set in PM1_UP_DLY (MSR
2000001Ah[15:8])), the GLMC starts accepting mem-
ory reads/writes.
6.1.3 BIOS Initialization Sequence
This is the recommended sequence that BIOS should take
to initialize the GLMC and DRAMs properly:
1) Initialize the following GLMC registers/bits based on
Serial Presence Detect (SPD) values:
— MSR 20000018h except REF_INT bits [23:8]
— MSR 20000019h
2) Initialize the following GLMC registers:
— MSR 2000001Ah[15:8] = C8h
— MSR 20002004h[2] = 0, [0] = 1
3) Release MASK_CKE[1:0] (MSR 2000001Dh[9:8] =
11).
4) Set/clear REF_TST bit (MSR 20000018h[3]) 16 times
to force 8 refreshes. This also causes a precharge-all
before the first refresh, per JEDEC requirement.
5) Initialize REF_INT (MSR 20000018h[23:8]) to set
refresh interval.
6) Perform load-mode with MSR_BA = 01 (MSR
200000018h[29:28] = 01) to initialize DIMM Extended
Mode register. Load-mode is performed by setting/
clearing PROG_DRAM (MSR 200000018h[0]).
7) Set RST_DLL (MSR 20000018h[27] = 1), perform sec-
ond load-mode with MSR_BA = 00 (MSR
20000018h[29:28]) to initialize Mode register and reset
DLL.
8) Perform third load-mode (MSR 20000018h[29:28] =
00) and RST_DLL cleared (MSR 20000018h[27] = 0).
9) Clear TRISTATE_DIS (MSR 2000001Dh[12] = 0) to
enable the GLMC TRI_STATE during idle cycles (i.e.,
CS[3:0]# = Fh).
10) Wait at least 200 SDCLKs before performing the first
read/write operation.