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200 AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.110 Memory Subsystem Array Control Enable MSR (MSS_ARRAY_CTL_EN_MSR)
The MSRs at addresses 00001980h-00001983h provide alternate array delay control values for the MSS arrays. After a
reset, the MSS clock modules provide JTAG-accessible control values. These MSRs can be used by software to override
these values.
5.5.2.111 Memory Subsystem Array Control 0 MSR (MSS_ARRAY_CTL0_MSR)
MSR Address 00001980h
Typ e R /W
Reset Value 00000000_00000000h
MSS_ARRAY_CTL_EN_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD EN
MSS_ARRAY_CTL_EN_MSR Bit Descriptions
Bit Name Description
63:1 RSVD Reserved. (Default = 0)
0EN Enable. Enable the array control values in this register to be used instead of those pro-
vided by the clock modules.
0: Disable.
1: Enable.
MSR Address 00001981h
Typ e R /W
Reset Value 00000000_2010F3C9h
MSS_ARRAY_CTL0_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD DMDATA1
313029282726252423222120191817161514131211109876543210
DMDATA1 DMDATA0 DMTAG1 DMTAG0 L2TLB1 L2TLB0
MSS_ARRAY_CTL0_MSR Bit Descriptions
Bit Name Description
63:36 RSVD Reserved. (Default = 0)
35:27 DMDATA1 Data Memory Subsystem Data 1 Delay Control. (Default = 04)
26:18 DMDATA0 Data Memory Subsystem Data 0 Delay Control. (Default = 04)
17:12 DMTAG1 Data Memory Subsystem Tag 1 Delay Control. (Default = F)
11:6 DMTAG0 Data Memory Subsystem Tag 0 Delay Control. (Default = F)
5:3 L2TB1 Data Memory Subsystem L2 TLB 1 Delay Control. (Default = 1)
2:0 L2TB0 Data Memory Subsystem L2 TLB 0 Delay Control. (Default = 1)