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330 AMD Geode™ LX Processors Data Book
Display Controller Register Descriptions
33234H
6.6.5.4 DC Vertical and Total Timing (DC_V_ACTIVE_TIMING)
This register contains vertical active and total timing information. The parameters pertain to both CRT and flat panel display.
All values are specified in lines.
15:12 RSVD Reserved. These bits should be programmed to zero.
11:0 H_SYNC_ST Horizontal Sync Start. This field represents the pixel clock count at which the CRT hori-
zontal sync signal becomes active minus 1.
Unlike previous versions of the DC, this field can be programmed to any pixel granularity;
it is not limited to character (8-pixel) granularity.
The horizontal sync must be at least 8 pixels in width, and cannot begin until at least 8
pixels after H_BLK_START (DC Memory Offset 044h[11:0]).
DC Memory Offset 050h
Typ e R /W
Reset Value xxxxxxxxh
DC_H_SYNC_TIMING Bit Descriptions
Bit Name Description
DC_V_ACTIVE_TIMING Register Map
313029282726252423222120191817161514131211109876543210
RSVD V_TOTAL RSVD V_ACTIVE
DC_V_ACTIVE_TIMING Bit Descriptions
Bit Name Description
31:27 RSVD Reserved. These bits should be programmed to zero.
26:16 V_TOTAL Vertical Total. This field represents the total number of lines for a given frame scan
minus 1. Note that the value is necessarily greater than the V_ACTIVE field (bits [10:0])
because it includes border lines and blanked lines. If the display is interlaced, the total
number of lines must be odd, so this value should be an even number.
15:11 RSVD Reserved. These bits should be programmed to zero.
10:0 V_ACTIVE Vertical Active. This field represents the total number of lines for the displayed portion of
a frame scan minus 1. Note that for flat panels, if this value is less than the panel active
vertical resolution (V_PANEL), the parameters V_BLANK_START, V_BLANK_END (DC
Memory Offset 054h[10:0, 26:16]), V_SYNC_START, and V_SYNC_END (DC Memory
Offset 058h[10:0, 26:16]) should be reduced by the following value (V_ADJUST) to
achieve vertical centering:
V_ADJUST = (V_PANEL - V_ACTIVE) / 2
If the display is interlaced, the number of active lines should be even, so this value
should be an odd number.
If graphics scaling is enabled (and interleaved display is disabled), this value represents
the height of the final (scaled) image to be displayed. The height of the frame buffer
image may be different in this case; DC_FB_ACTIVE (DC Memory Offset 05Ch) is used
to program the horizontal and vertical active values in the frame buffer when graphics
scaling is enabled.
If interleaved mode is enabled, this value represents half the height of the final (scaled
and interleaved) displayed image.